Field of the Invention
The present invention relates to a semiconductor memory configuration addressed via word lines and bit lines and having a memory cell array containing a multiplicity of memory cells and redundant memory cells. The redundant memory cells, in the event of failure of the memory cells of the memory cell array, replace the memory cells as spare memory cells, the memory cells of the memory cell array and the spare memory cells being provided on a semiconductor chip.
Semiconductor memory configurations, such as, for example dynamic random access memories (DRAMs), cannot, in practice, be fabricated without failure of memory cells in the memory cell array. This is primarily due to the impinging of undesirable particles during wafer processing in the course of the fabrication of the semiconductor memory configuration, and also to other reasons, such as short circuits, etc. In order to be able to overcome the problems associated with this, therefore, use is generally made of redundant memory cells with redundant bit lines and word lines which can replace memory cells that have failed in this way.
In practice the procedure is such that after the fabrication of a DRAM, still at the wafer level, a test is performed which is intended to localize all failed memory cells of the DRAM. Such failed memory cells may be individual memory cells, groups of memory cells or even complete bit lines and word lines with the corresponding memory cells. Once the failed memory cells have been identified, which is done via a corresponding addressing, the addresses of the failed memory cells and, if appropriate, groups of memory cells and also word lines and bit lines are stored in an external computer. The external computer then carries out a complicated calculation involving the failed memory cells, on the one hand, and the available spare memory cells, on the other hand. In this case, "memory cells" should, of course, also be understood to be groups of memory cells and also, if appropriate, entire word lines and bit lines with corresponding memory cells. This calculation determines how the failed memory cells can be replaced by the spare memory cells in an optimum manner. The calculation is extremely complex, this being due in no small part to the fact that the highest possible yield is striven for. In other words, the failed memory cells are intended to be replaced by the redundant memory cells in such a way that as few redundant memory cells as possible are required, that is to say that the number of spare memory cells is intended to be kept small.
On account of the complicated calculation, to date no thought has been given to using built-in-self-test (BIST) technologies precisely in the case of DRAMs, even though BIST per se has been used for a relatively long time in microelectronics. This is because with BIST, the necessary calculations for optimum use of the redundant memory cells instead of the failed memory cells cannot be performed without a great deal of area being taken up on the wafer. In other words, these calculations presuppose a BIST computing unit, the area requirement of that by far exceeds the acceptable amount in the context of fabricating DRAMs.
Thus, a problem is presented which at first sight appears to be irresolvable. In the context of assigning the redundant memory cells as spare memory cells to the failed memory cells, the use of an external computer is complicated and should be avoided if possible. Recourse to the inherently widespread BIST technology is not possible, however, since using this technology would result in taking up too much area on the wafer of the semiconductor memory configuration. For this reason, to date no thought has been given to using BIST technology in the context of fabricating DRAMs in order to replace failed memory cells by redundant memory cells.